Network software for Tessent TestKompress simplifies DFT flow

The software includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip level test delivery resources. According to Mentor, this enables a bottom-up DFT flow that can simplify DFT planning and implementation, while at the same time, reducing test time up to a factor of four. It also has support for tiled designs and optimisation for identical cores, making it suitable for large emerging compute architectures.

The bus-based scan distribution architecture enables simultaneous testing of a number of cores. Test time is shortened by high-speed data distribution handling imbalances between cores and a number of identical cores can be tested. Each core has a plug-and-play interface which is claimed to simplify scan timing closure and is suitable for abutted tiles.

Each design block has a series of host nodes, each distributing data between the network and the test structures in the block. The software automates the implementation, pattern generation, and failure reverse mapping processes. DFT test resources can be optimised for each block without impacting the rest of the design. The optimised handling of identical cores reduces the implementation process, while eliminating waste in the test data and multiplexing enables “substantial reductions” in test data time and volume, says the company.

Support for Tessent Streaming Scan Network technology in Tessent TestKompress provides scalable test access  for the next generation of advanced IC designs. The Streaming Scan Network software is compatible with all Tessent DFT products and can be combined with Tessent Diagnosis cell-aware and layout-aware diagnosis for end-to-end defect detection and diagnosis, advises the company. All Tessent DFT products are qualified for all ASIL ISO 26262 projects with a complete set of certified ISO 26262 documentation.